`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/07/06 16:28:00
// Design Name: 
// Module Name: mem_data
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mem_data(
    clk,reset_n,op_w,addr,data_in,data_out
    );

    input clk;
    input reset_n;
    input op_w;
    input [31:0] addr;
    input [31:0] data_in;
    output [31:0] data_out;

    reg [7:0] mem_data [31:0];

    always @(negedge clk,negedge reset_n) begin
        if(~reset_n) begin
            {mem_data[0],mem_data[1],mem_data[2],mem_data[3]} <= 32'b000000000000000000000000000110;
        end
        else begin
            if(op_w)
                {mem_data[addr],mem_data[addr+1],mem_data[addr+2],mem_data[addr+3]} <= data_in;
        end
    end

    assign data_out = {mem_data[addr],mem_data[addr+1],mem_data[addr+2],mem_data[addr+3]};

endmodule
